JEDEC has released its new specification that aims to push down the pricing of the ultra-expensive HBM that powers the fastest AI processors. While the new standard will not help relieve the DRAM shortage as it uses large HBM4 DRAM devices, it can make high-bandwidth memory a bit cheaper as it enables attaching SPHBM4 memory stacks without advanced packaging and using inexpensive organic substrates.

The standard's body published the specification of SPHBM4, Standard Package High Bandwidth Memory (JESD330-4), that combines HBM4 DRAM ICs with standard packaging and a fast 'narrow' 512-bit interface. Here are the details.

HBM4 performance with a 512-bit wide interface

Although 1024-bit and 2048-bit interfaces used by HBM3 and HBM4 memory deliver unbeatable performance, their wide interfaces consume significant silicon area inside processors, they require expensive interposers, and advanced packaging technologies with limited capacity, such as TSMC’s CoWoS, for integration with host processors. The upcoming SPHBM4 memory continues to use the same HBM4 DRAM stacks as JESD270-4, but swaps the conventional HBM base die for a new SPHBM4 PHY/buffer die featuring a narrower 512-bit interface that enables mounting on standard organic substrates without using sophisticated packaging methods for integration. To offset the effect of the narrower interface, SPHBM4 supports considerably higher data transfer rates ranging from 22.4 GT/s to 46.0 GT/s.

Instead of connecting to the host processor using a 2048-bit memory interface like HBM4, SPHBM4 uses 32 independent 16-bit DDR channels organized into eight Quad Channels. Since 'Quad Channel' is a new term, let us explain how things work. Internally, an HBM4 stack contains 32 memory channels, each 64 bits wide, for a total external interface width of 2048 bits. SPHBM4 needs to 'convert' the 2048-bit internal I/O onto a 512-bit external interface, which is why it groups every four HBM4 channels into a Quad Channel. As a result, externally, a Quad Channel exposes 64 data pins (4 × 16 bits), which replace the 256 data pins (4 × 64 bits) that those four HBM4 channels would normally require. To preserve bandwidth, these 64 pins operate at four times the data rate of the original HBM4 interface.

While SPHBM4 dramatically increases I/O bandwidth, it does not make the DRAM array itself faster. The HBM4 memory core retains the same fundamental architecture and timings, including core frequency, row activation, precharge, and refresh operations, though the additional PHY is expected to introduce some latency. For example, the DRAM core runs at only one-quarter of the external interface frequency, which means 2 GHz in the case of SPHBM4 with a 32 GT/s speed bin.

The major change is the new base die, which implements a high-speed SerDes-like PHY that maps each 16-bit external channel to four conventional 64-bit HBM4 channels. As a result, SPHBM4 introduces equalization, lane training, BER requirements, and other high-speed signaling features that are unnecessary in HBM4’s slower, wide parallel interface. To support transfer rates of up to 46.0 GT/s/s per pin, each Quad Channel uses a shared command/address interface protected by forward error correction (FEC), while data transfers rely on dedicated differential write (WCK) and read (RCK) clocks, as well as ECC and error-reporting signals.

When it comes to capacity, SPHBM4 can use stacks containing 4, 8, 12, or 16 DRAM dies featuring 24 Gb or 32 Gb densities, so the largest standardized SPHBM4 configuration is a 64 GB memory stack built from sixteen 32 Gb DRAM dies, identical to the maximum capacity supported by HBM4E.

Cheap HBM at last?

The standard supports bump pitches greater than 90 µm and channel reaches up to 20 mm, which are two features that enable dropping the expensive interposer and using less-expensive organic substrate routing. However, getting rid of the interposer and CoWoS (or similar) packaging does not automatically make SPHBM4 inexpensive. SPHBM4 still requires massive HBM4 DRAM ICs, 2.5D packaging, a complex base die (which is likely costlier than the one used by conventional HBM4), and advanced package assembly with through-silicon vias. In addition, SPHBM4's narrow interface consumes significantly less die perimeter and silicon area inside processors, which makes it more attractive to companies that strive to install more compute capability and/or intend to install more memory stacks around their processors. However, we are still talking about a niche high-performance memory technology that will address select applications and will barely rival HBM4 directly.

When it comes to maximum performance, HBM4 moves the data at 8 GT/s (though most controllers and chips support higher data rates), so one HBM4 stack can offer bandwidth of 2 TB/s. HBM4E is set to up data transfer rate to 12 – 12.8 GT/s, therefore increasing peak bandwidth to 3 – 3.3 TB/s per stack. By contrast, one SPHBM4 with a 46 GT/s interface can hit 2.944 TB/s, though do not expect the initial versions of SPHBM4 to hit the maximum speed. Therefore, it is likely that HBM4, HBM4E, and C-HBM4E will maintain a performance lead in terms of bandwidth over SPHBM4 in the foreseeable future.

HBM4 latency will still probably have an edge over SPHBM4. HBM4 essentially connects to its host processor almost directly through a very simple interface. By contrast, SPHBM4 inserts a much more sophisticated PHY that performs serialization/deserialization, lane training, FEC handling, and other operations that can add a few nanoseconds of latency. This may not be a big problem for some applications, but inference benefits a lot from low latencies.

When it comes to power and voltages, HBM4 and SPHBM4 share the same DRAM core voltage because SPHBM4 reuses standard HBM4 DRAM stacks. However, I/O is different: HBM4 leaves the interface voltage up to memory vendors and allows implementations at 0.7V, 0.75V, 0.8V, or 0.9V, depending on the desired balance between power, speed, and signal integrity. By contrast, SPHBM4 standardizes the external I/O at 0.75V.

Also, HBM4 moves data over a very wide interface with many slow parallel links that tend to be very energy efficient. By contrast, SPHBM4 moves the same amount of data through one-quarter as many wires, which run roughly four times faster. High-speed data transfer tends to be less energy efficient than 'slow' data transfers over a wide interface. Keeping in mind SPHBM4's rather sophisticated PHY that converts a wide interface into a narrow interface, which is likely a power-hungry process. Nonetheless, the 4X lower number of drivers and receivers could tangibly reduce the power consumption of SPHBM4. That said, without implementation details from DRAM makers or a processor developer, it is impossible to conclude which memory type has lower power consumption.

Last but not least, SPHBM4 essentially trades manufacturing challenges that arise from using silicon interposers for an engineering challenge of developing an extremely sophisticated base die/PHY. Developing and manufacturing such a base die should not be a problem for foundries. However, it remains to be seen whether DRAM makers can design and produce SPHBM4 with decent power efficiency. After all, both Micron and SK hynix work with TSMC to build C-HBM4E and HBM4E base dies, whereas Samsung's memory division uses base dies produced by Samsung Foundry.

China factor

One interesting aspect of SPHBM4 is whether Chinese developers of AI accelerators can benefit from this technology. In theory, Chinese developers like Biren, Huawei, Moore Threads, and other blacklisted companies that cannot use TSMC's chip manufacturing or packaging services could become one of the biggest beneficiaries of SPHBM4, perhaps even more so than the U.S.

First up, a smaller shoreline directly benefits chips that are made using trailing nodes, as it enables packing more compute capability into them without sacrificing memory bandwidth or capacity. Secondly, Chinese OSATs currently do not offer CoWoS-like technologies, so eliminating the interposer and using advanced organic substrates is a benefit.

However, SPHBM4 still requires HBM4 DRAM stacks, and today, Samsung, SK hynix, and Micron are the only companies capable of producing them, while China-based CXMT can barely make HBM2E. Furthermore, building a 46 GT/s PHY is very hard and will likely be challenging for Chinese IC developers.

Nonetheless, assembling SPHBM4 packages on organic substrates is arguably more aligned with China's existing manufacturing base, so if local DRAM makers eventually develop competitive HBM4-class memory, SPHBM4 could substantially reduce one of the country's remaining infrastructure gaps.

Summary

JEDEC's SPHBM4 looks like a promising standard that can potentially address a broader range of applications than HBM4 itself due to lower integration cost. Still, HBM4, HBM4E, and C-HBM4E will maintain performance leadership, which will make them a preferable choice for flagship AI accelerators in the coming years.

ChangXin Memory Technologies, or CXMT, has just received official validation from MSI for its high-speed DDR5 memory modules. The manufacturer has released new beta BIOSes across its AM5 lineup, unlocking stable frequencies up to 8,200 MT/s for 3GB CXMT chips on dual-DIMM motherboards. Previously, RAM using these modules was limited to around 6,800 MT/s despite the hardware itself being capable of much more.

The test BIOS comes from MSI China — there's no announcement on global channels for some reason, and it's only available for select motherboards at the moment. MSI tested region-bound retail kits from Lexar and KingBank on boards with both two slots and four slots, but we only have screenshots for the former, courtesy of Videocardz.

One test was conducted using 24GB sticks (2x24) on the MEG X870E Unify model and a Ryzen 7 9700X CPU. This was mostly a standard kit since it came with a 6,000 MT/s EXPO profile. The other config consisted of 16GB sticks (2x16) with an EXPO profile already running at 7,200 MT/s, so it was somewhat cherry-picked silicon, paired with a Ryzen 5 9600X on a MAG B850 MPower motherboard.

The results showed that on dual-DIMM motherboards, 24Gbit (3GB) modules from CXMT were able to clock up to 8,200 MT/s, passing MemTest with 101% coverage. Conversely, 16Gbit (2GB) chips were also stable at 8,000 MT/s on the same test bench with 101% coverage. Moving over to quad-DIMM, the patch notes for the BIOS say they've "also been raised to DDR5-7200," where the limit was stuck at 6,800 MT/s prior.

This is not the first time MSI has optimized Chinese RAM for some of its motherboards. Earlier this year, the company did the same thing for Intel's 800-series models in China. Anyway, these specific BIOSes are meant for the AM5 socket and they're based on existing stable releases — just patched with unlocked memory overclocking features. More motherboards should be supported soon, but for now you can check out the MSI China's community release channel if you want to try one yourself.

Memory prices will keep climbing through the third quarter of 2026, but the blistering increases of the past few quarters are set to cool as consumer buyers reach the ceiling of what they can afford, according to a detailed TrendForce report. The research firm's latest memory pricing survey projects conventional DRAM contract prices to rise 13% to 18% quarter-over-quarter (QoQ) in Q3 2026, with NAND Flash contract prices increasing 10% to 15%; substantial gains, but a marked slowdown from the roughly 60% jumps recorded in the second quarter.

According to the report, the cooldown is driven by consumer electronics manufacturers' unwillingness and inability to absorb higher memory costs after months of relentless price increases, rather than by improved supply. In other words, memory remains in short supply, but consumers are no longer willing to keep paying ever-higher prices.

AI continues to be the market's driving force. Demand for AI inference systems and hyperscale data centers remains strong enough to keep both DRAM and NAND supply constrained, while memory manufacturers continue shifting production capacity toward higher-margin server products. This leaves less capacity available for consumer memory, preventing prices from falling even as demand from PCs and smartphones weakens.

As a result, the memory market is increasingly split between enterprise and consumer customers. On the server side, TrendForce expects demand to remain healthy through 2027 as improving CPU availability supports continued deployments of AI servers built around x86 processors and registered DIMMs (RDIMMs). Although server DRAM is expected to remain undersupplied during the third quarter, price increases should moderate because a portion of purchases is covered by long-term supply agreements.

Consumer markets appear to paint a very different picture. Notebook manufacturers are expected to keep replenishing inventories, but higher memory costs are gradually feeding through into retail pricing, a trend TrendForce believes could weigh on PC shipments for the rest of the year. Smartphone vendors face similar pressure, with many expected to raise handset prices to offset persistently high LPDRAM (low-power DRAM) costs while simultaneously becoming more cautious with production plans as consumer demand softens.

The same pattern is beginning to emerge across storage products. PC manufacturers accumulated substantial client SSD inventories during the first half of 2026, reducing their willingness to accept another round of price increases. Suppliers have responded by taking a more flexible approach during contract negotiations, helping to moderate SSD pricing even as enterprise storage continues to benefit from AI infrastructure spending.

Not every segment is seeing the same level of demand. TrendForce notes that NVIDIA's RTX PRO 6000 Blackwell has yet to generate the expected wave of GDDR7 demand, while weaker notebook shipments have also softened demand for graphics memory. At the opposite end of the market, retail products such as USB flash drives and memory cards remain sluggish as higher upstream costs become increasingly difficult to pass on to consumers.

For PC builders, the report suggests that meaningful price relief is still some way off. Memory prices are continuing to rise because AI infrastructure remains the industry's top priority. However, the pace of those increases is slowing as consumer demand reaches its breaking point.

17 plaintiffs sued Samsung, SK hynix, and Micron in the U.S. District Court for the Northern District of California in late June, alleging the three companies, which together control roughly 90% of the global DRAM market, coordinated supply restrictions that pushed memory prices up around 700% in four years. The complaint is the third major legal assault on the DRAM industry in two decades. The first ended in criminal guilty pleas, roughly $730 million in fines, and prison terms for executives. The second collapsed in 2020; this new case must clear the same legal barrier that killed it.

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A cartel conviction, then a failed sequel

Between 1998 and 2002, DRAM makers fixed the price of memory sold to Dell, HP, Compaq, IBM, Gateway, and Apple, leading to a landmark case that saw the Department of Justice extract guilty pleas across the sector: $300 million from Samsung in 2005, then the second-largest criminal antitrust fine in U.S. history, alongside $185 million from Hynix, $160 million from Infineon, and $84 million from Elpida. More than a dozen execs served prison time in the U.S., while Micron, which admitted participating, escaped prosecution entirely by turning first under the DoJ's corporate leniency program.

Then, in 2018, Hagens Berman filed a class action alleging the same three companies colluded during the 2016-2017 upcycle, when DRAM prices roughly doubled and all three throttled supply growth in lockstep. The district court dismissed it in 2020, and the Ninth Circuit affirmed that decision in 2022, ruling the alleged conduct was “more likely explained by lawful, unchoreographed free-market behavior” than by agreement. The plaintiffs never reached the discovery phase in that case; it instead died on the pleadings, which is where this latest case is also likely to be decided.

Parallel conduct is legal

Section 1 of the Sherman Act punishes agreements in restraint of trade, but not identical behavior. When three firms in a concentrated market watch each other's earnings calls and rationally match each other’s output cuts, antitrust law calls it conscious parallelism and permits it.

Since the Supreme Court’s 2007 Twombly decision, a price-fixing complaint can overcome a motion to dismiss only if its factual allegations make an actual agreement plausible, not merely possible, and parallel conduct alone can never reach that threshold. Instead, plaintiffs need what are known as “plus factors”: actions against each firm's independent self-interest, suspicious communications, or opportunities to conspire that produce otherwise inexplicable behavior.

In the 2018 case, the plaintiffs offered eight plus factors, including trade-press statements about supply discipline and attendance at the same industry events, and both courts found them consistent with each company independently deciding that flooding a recovering market would be stupid. An oligopolist declining to start a price war isn’t evidence of a cartel; it’s evidence of an oligopoly.

2026's HBM pivot

What’s new in this case is that the complaint alleges the three memory makers used their pivot to high-bandwidth memory as a coordinated pretext to gut commodity DRAM output, curtailing DDR3 and DDR4 production far beyond what HBM demand required and starving the market that feeds PCs, phones, and servers.

The filing stacks supporting plus factors on top, including near-simultaneous production cuts announced in late 2022, Micron's decision last year to shut down its consumer-facing Crucial memory business and remove a retail supply channel, and the makers' synchronized customer-vetting regime introduced to block hoarding and resale, which the plaintiffs read as jointly policing who gets supply. Apple’s memory-driven iPad and Mac price increases appear in the complaint as downstream proof of harm.

HBM carries far higher margins than commodity DRAM, and every maker had an independent incentive to chase Nvidia’s order book. The late-2022 cuts came during the worst memory downturn in over a decade, when SK hynix and Micron were posting operating losses, and Samsung held out on cuts months longer than its rivals, which is awkward material for a case looking to rely on a lockstep narrative. Crucial's shutdown also coincided with Micron reallocating output toward data center customers paying more. As such, every allegation in the complaint has a non-conspiratorial explanation available, and under Twombly, the plaintiffs need there to be at least a plausible conspiracy theory to have a chance of success.

Motions to dismiss likely

A leading-edge DRAM fab costs $15 billion to $20 billion and takes years to bring up, so no fourth player can arbitrage the shortage away on any timescale that’s relevant to this case. Three firms facing inelastic demand and no threat of entry can sustain supracompetitive prices through nothing more than mutual self-restraint, and current numbers show what that looks like.

SK hynix reported a record operating margin above 70% in its most recent quarter, and the investment firm Jefferies expects DRAM contract prices to rise another 40% to 50% in the third quarter and 30% to 40% in the fourth, with no meaningful relief before 2028. SK Group chairman Chey Tae-won has put the end of the shortage even further out. Margins that fat are indeed consistent with a cartel, but they’re equally consistent with a demand shock hitting a market built to under-supply, and courts have declined to let juries choose between the two unless a seriously high evidential threshold has been reached. Here, that doesn’t appear to have happened. In addition, China’s CXMT is rapidly expanding DDR5 output with state backing, and any sustained market share gains and price pressure from it would undercut the complaint's premise that the incumbent big three face(d) no competitive pressure.

The defendants haven’t yet responded in court and are likely to file motions to dismiss. Surviving dismissal would force three companies, which are enjoying the most profitable memory cycle in history, to open their internal communications regarding HBM allocation and commodity wind-downs to plaintiffs’ lawyers for the first time. If the court follows the Ninth Circuit's 2022 reasoning instead, the suit joins its predecessor, and 90% of the world's DRAM supply continues to be governed by three firms whose parallel restraint, in the law’s eyes, remains just good business.

SK hynix this week announced that it would invest an additional KRW 100 trillion ($64 billion) in its Cheongju campus to expand production of 3D NAND and HBM packaging at the site. Given the vast investment, expect the company to add some massive production capacity, but unfortunately that production capacity is going to kick in only several years down the road. But that investment pales in front of the company's plan to invest $712.5 billion in its South Korean operations.

The massive KRW 100 trillion ($64 billion) in its Cheongju campus investment is only a part of SK hynix's grand plan to invest KRW 1.1 trillion ($712.5 billion) in a variety of projects in South Korea. In particular, the company intends to invest KRW 400 trillion ($259.5 billion) in its all-new Southwestern semiconductor cluster as well as KRW 600 trillion ($389.3 billion) in its Yongin site. While the Cheongju investment is considerably lower than investments in other campuses, it is the only project that is actually detailed enough.

$64 billion go to Cheongju to support NAND and packaging

SK hynix claims that it intends to build a 3D NAND fab, install manufacturing equipment, and expand its advanced packaging capabilities for HBM back-end processing at its Cheongju campus in the Chungcheong region. The company intends to start building its M17 fab next year, so the earliest timeframe it comes online is sometimes in 2029 at the earliest. The fab will cost around KRW 80 trillion ($51.8 billion), whereas the new P&T7 packaging and test facility will cost KRW 20 trillion ($12.945 billion).

SK hynix's campus in Cheongju houses some of the company's primary fabs that manufacture 3D NAND flash, including M11, M12, and M15, and historically it was the company's main 3D NAND memory manufacturing center. However, because multi-layer 3D NAND and high-bandwidth memory (HBM) stacks use similar packaging technologies, it is now evolving into a site that also makes HBM stacks: M15X produces actual DRAM dies, whereas P&T3 performs packaging operations.

But the investment in SK hynix's Cheongju NAND and HBM assembly operations pales when compared to how much money the company plans to pour into other projects.

$389.3 billion go to Yongin Semiconductor Cluster to boost DRAM output

SK hynix plans to invest approximately $389.3 billion in the Yongin Semiconductor Cluster, which is the company's largest investment commitment ever and which will make the campus its largest DRAM production site. Meanwhile, Yongin is a greenfield site today.

The first fab in Yongin is expected to commence operations in May 2027, while the remaining fabs will be added sequentially. It takes about a year or 1.5 years or so to fully ramp a DRAM fab, so expect the facility to impact the memory market in 2028 – 2029. Under the company's newly announced plan, construction of all four fabs is now targeted to complete the fourth fab by 2033, instead of the original 2045 timeline. The $389.3 billion investment extends beyond 2033.

$259.5 billion go to Southwestern Semiconductor Cluster

Unlike Yongin, the Southwestern Semiconductor Cluster does not even exist. It is currently a planned project, and SK hynix has not even selected a specific site within southwestern Korea. The company says the exact location will be determined after evaluating land availability, electricity, water, transportation, and other infrastructure requirements in consultation with central and local governments.

The cluster is envisioned as SK hynix's next major manufacturing base after Icheon, Cheongju, and Yongin. For now, the planned investment totals approximately $259.5 billion, though given that the project's completion is decades away, we can expect that number to change upwards or downwards depending on the market conditions and the cost of wafer fabrication equipment.

The investment will be phased over many years and cover land acquisition, fab construction, and production tools. SK hynix says preparations must begin now because developing a new semiconductor cluster — including site selection and infrastructure — takes many years. For example, development of the Yongin Cluster took about nine years, according to SK hynix.

Not alone

SK hynix is not alone in investing in South Korea. Samsung on Thursday announced plans to spend some KRW 140 trillion ($90.98 billion) in its operations in South Korea’s Chungcheong region.

Under the plan, Samsung Display will expand OLED production in Asan; Samsung Electronics will build five HBM production lines in Onyang and modernize HBM-related facilities in Cheonan; Samsung SDI will establish a battery production line in Cheonan to validate next-generation technologies before deploying them globally; and Samsung Electro-Mechanics will expand AI server package substrate manufacturing in Sejong.

The price of DDR5 memory is setting new highs these days as demand badly outstrips supply. In a bid to save money, Meta is recovering legacy DDR4 memory from used servers and is installing it into new machines using its in-house developed Vistara ASIC that enables it to connect old memory modules to its latest servers running AMD EPYC 'Turin' processors that only support DDR5 memory.

Interestingly, Meta is not the only company developing such a solution. Panmnesia, a startup from South Korea, has developed an off-the-shelf CXL controller and switch that enables servers to attach considerably larger memory pools without extending latency, which differentiates Panmnesia’s solution from competing CXL offerings.

Custom ASIC enables DDR4 memory to work with new servers

Vistara is Meta’s first-gen custom CXL memory expander ASIC designed to attach outdated DDR4 memory to modern servers. The chip implements a CXL 2.0 Type-3 memory expander over a PCIe 5.0 x16 interface and bridges standard DDR4 RDIMMs to host processors. Each ASIC supports two independent 72-bit DDR4 memory channels and can provide up to 256 GB of capacity using 64 GB DIMMs. At present, Meta deploys 128 GB per ASIC using 32 GB DDR4 modules recovered from decommissioned servers.

Meta deploys Vistara in its MemServer platform, where two ASICs connect to a single 158-core AMD Turin processor over PCIe 5.0 x8 links. Each server combines 768 GB of DDR5-6400 local memory with 256 GB of CXL-attached DDR4-2400, which expands memory capacity to 1 TB. The software stack transparently exposes CXL memory as a separate NUMA node and enables Linux to migrate cold pages to the slower DDR4 tier (with 76 GB/s of bandwidth) and retain frequently accessed data in local DDR5 (with 614 GB/s of bandwidth).

The ASIC is based on three RISC-V processor cores for secure boot, device initialization, firmware management, and health monitoring. Meta claims it has optimized its CXL controller and memory pipeline to reduce protocol overhead, minimize queuing delays, and lower idle round-trip latency to around 50ns. The chip also incorporates advanced reliability features, including Reed-Solomon two-symbol error correction and x4 chip-kill support.

Not only Meta's Vistara

Meta is not the only company that wants to attach legacy DDR4 memory to newer servers that rely on DDR5 memory and save some money. While Vistara is available exclusively to Meta, there is a new CXL expander solution from Panmnesia that will be available to other companies.

"There has been a perception that putting a switch between the CPU and devices makes it hard to meet the memory-access latency these systems expect, so directly attached multi-headed devices (MHDs) stayed the norm even though they were harder to scale," said Myoungsoo Jung, chief executive of Panmnesia. "Our work shows this is not an inherent limit of CXL or CXL switches — it is a trait of early-stage CXL, and one that fades as the standard and the products around it mature. With a fabric switch that carries our next-stage CXL controller, scalability, low latency, and stable performance can come together."

CXL is a protocol that sits on top of the PCIe physical interface. As a result of this, many early CXL implementations were built by modifying existing PCIe IP, which is why such implementations inherited architectural characteristics optimized for PCIe rather than for memory-semantic communications, which added substantial latency, according to Panmnesia. By contrast, its new CXL controller IP features a redesigned data path that replaces separate per-layer buffers with shared buffers to eliminate much of the synchronization overhead. In addition, it features additional latency optimizations throughout the protocol stack that offset the additional hop introduced by the switch.

The accompanying CXL fabric switch introduces Port-Based Routing (PBR), which removes the tree-topology limitations of conventional Hierarchy-Based Routing (HBR) used by PCIe and early CXL implementations. The fabric switch still supports both PBR and HBR to enable flexible system topologies, optimized traffic routing, and stable performance. In practice, it enables companies like Meta to install more DDR4 memory into their modern servers without major performance degradation because of high latency.

Panmnesia claims that while early CXL deployments could connect only a handful of compute nodes to shared memory pools, its fabric scales to up to 64 nodes, which means greater flexibility for hyperscalers that tend to run thousands of servers, but which now have to rationalize usage of expensive DRAM.

Panmnesia says its next-generation CXL technologies are progressing toward commercialization. The company has pre-release silicon for its PCIe 6.4/CXL 3.2 Fusion Switch and has completed development of its PCIe 7.0/CXL 4.0 Combo IP, which supports the latest features introduced by the CXL 4.0 specification.

Edit 07/02/2026 1:00 am ET: Corrected the DRAM voltages and pricing with new information provided by G.Skill.

G.Skill’s AMD EXPO ULL (Ultra Low Latency) memory kits, strong contenders among today's best RAM options, have arrived on the retail market. While AMD previously stated that EXPO ULL memory kits would be “effectively the same price” as vanilla EXPO memory kits, this has proven by far not to be the case. In reality, these new EXPO ULL kits carry a substantial premium that can scale up to 80% over their regular counterparts, according to the latest Newegg listings.

The Trident Z5 NeoX is G.Skill’s latest memory series featuring ULL optimizations. The new lineup is available in three striking color options, black, glossy black, and white, that cater to a variety of system aesthetics. G.Skill has not released the official product pages for the Trident Z5 NeoX series, so detailed information on the full range of planned capacities and speeds is unavailable. Newegg is currently selling the Trident Z5 NeoX memory kits in a 32GB (2x16GB) dual-channel configuration clocked at DDR5-6000.

To make it a meaningful comparison, we compared the Trident Z5 NeoX memory kits to their direct counterparts, the standard Trident Z5 Neo series. We deliberately excluded similarly specced lineups such as the Aegis or Ripjaws series, which are tailored for budget-conscious buyers, as well as omitting the Trident Z5 Royal Neo, which targets a more posh crowd.

According to G.Skill, the EXPO ULL memory kits share similar pricing to the non-ULL counterparts. However, there may be a price difference between ULL memory kits and regular memory kits in stores. The reason is that some retailers likely still have older inventory that was bought at a lower cost. They may try to balance the prices of new and old stock, resulting in the price gap. This may occur specifically when prices are on the rise.

According to Newegg, the Trident Z5 NeoX DDR5-6000 C26 memory kit presently carries a 57% premium over the standard Trident Z5 Neo DDR5-6000 C26 memory kit. The price gap widens further for the DDR5-6000 C28 variant, which commands a 79% premium. Meanwhile, the Trident Z5 NeoX C30 and C36 versions are 14% and 9% more expensive than their regular Trident Z5 Neo counterparts, respectively.

On a superficial level, it’s basically impossible to grasp the true extent of the level of optimization that goes into AMD EXPO ULL memory kits just by looking at product listings. It’s customary for memory manufacturers and retailers to only list the four primary memory timings: CAS Latency (CL), Row Address to Column Delay (tRCD), Row Precharge Time (tRP), and Row Active Time (tRAS). Unfortunately, these memory timings only tell part of the story, since most of the secondary timings for AMD EXPO ULL certification, including Refresh Interval (tREFI), Row-to-Row Delay Short (tRRDS), and Write Recovery Time (tWR), are not publicly visible.

Returning to the example of the Trident Z5 NeoX memory kits, what immediately stands out is the dramatically reduced tRAS value, which is up to 67% lower than that of standard Trident Z5 Neo memory kits. In short, tRAS dictates how many clock cycles must pass after a row opens before the memory controller can close it. The reason for high tRAS values in DDR5 resides in the architecture itself. Unlike DDR4, which operates with a single 64-bit channel, DDR5 employs two independent 32-bit subchannels. This change, alongside the doubling of burst length from BL8 to BL16, enables each memory command to transfer twice as much data through the channels in a single operation. As a result, the memory rows remain open longer, leading to the higher tRAS values typically seen in DDR5 modules. What makes the AMD EXPO ULL memory kits unique is that they drive tRAS values back down to levels reminiscent of high-performance DDR4 from the old days.

Another significant advantage of AMD EXPO ULL memory kits is their ability to maintain tight timings at the same voltages. Lower DRAM voltages translate to lower power consumption, lower operating temperatures, and more headroom for overclocking.

If you’re looking for the simplest explanation as to why AMD EXPO ULL memory kits carry a hefty premium over regular AMD EXPO memory kits, it boils down to the extensive optimization and meticulous binning process involved in their production. Memory vendors spend more time testing and sorting memory chips that can operate at the tightest timings and lowest voltages. It’s a very time-consuming and labor-intensive process. As a result, the overall manufacturing costs for EXPO ULL kits are higher than for standard kits. In many ways, you aren’t just paying a premium for the hardware itself, but also for the vendor’s time and the guarantee that the memory modules run at near-maximum potential right out of the box.

Hardware enthusiasts, server administrators, and all regular readers of this site will be well aware of the ongoing "RAMpocalypse," the memory and storage shortage affecting nearly every market and raising prices across the board in the tech sector. If you were hoping for relief, don't hold your breath; at the International Supercomputing Conference this past week, Lenovo reportedly said "it will never be like it was last year." Underlining the point, one of Lenovo's presentation slides was titled "The 5 Step RAMaggeddon Survival Guide."

That comes to us by way of our German friends over at ComputerBase, who note that "never" was said with a smirk, thus implying that it wasn't meant to be taken literally. Instead, the message from Lenovo is that memory prices were unusually low in early 2025, and it will be a long time before we see comparatively low prices on RAM, flash memory, and other components, as the #1 worldwide PC OEM expects AI demand to continue growing.

According to ComputerBase's report from ISC 2026, Lenovo's broader message is that the economics of the memory industry have fundamentally changed. The company reportedly argued that even as significant new manufacturing capacity comes online beginning around 2028, demand from AI infrastructure is expected to absorb much of that additional output, preventing DRAM and NAND prices from returning to the lows seen over the past two years.

The report points to SK hynix's recently announced plans to triple its memory production capacity by 2034 as supporting evidence. Lenovo's reasoning is straightforward: the notoriously profit-hungry memory manufacturers would be unlikely to invest so heavily in expanding production if they expected a return to the razor-thin margins and oversupply that characterized parts of the market in early 2025.

In case you needed extra evidence for its argument, Lenovo also suggested that memory capacity itself is becoming an increasingly important consideration when designing and purchasing servers. While vendors have traditionally advertised the maximum supported memory capacity of new platforms, actually populating those DIMM slots has become far more expensive. New dual-socket servers are on the way next year with 16 memory channels per processor, meaning that even a relatively modest configuration can require around 1 TB of installed memory to fully utilize the available bandwidth.

Lenovo is far from the only company predicting a prolonged memory crunch, although the industry's incentives are worth keeping in mind. Micron recently told investors it expects supply to remain constrained through at least 2027, with only gradual improvement beginning in 2028, while SK hynix has warned the shortage could persist until around 2030 as AI infrastructure continues absorbing wafer capacity. Those forecasts are backed by multi-year supply agreements worth roughly $100 billion that Micron has already signed with customers, underscoring how seriously hyperscalers are treating long-term memory availability.

Even companies that traditionally wield enormous purchasing power are feeling the squeeze. Apple reportedly has sought permission from the U.S. government to source DRAM from Chinese memory maker CXMT, a Pentagon-blacklisted company, illustrating just how valuable additional memory supply has become as prices continue to climb. At the same time, memory vendors are enjoying some of the strongest pricing power (and profit margins) they've seen in years, giving them little incentive to accelerate a return to the boom-and-bust pricing cycles that once defined the DRAM market.

Ironically, one consequence of the ongoing memory shortage is that HBM is becoming more economically attractive relative to conventional system memory. DRAM manufacturers have redirected significant production capacity toward higher-margin HBM for AI accelerators, reducing the supply of commodity DDR5 and LPDDR5 while demand for both remains elevated. As a result, the premium for HBM-backed computing has narrowed, not because HBM has become inexpensive, but because traditional system memory has become dramatically more expensive. Hyperscalers were going to buy the GPUs anyway, so maximizing their utilization to reduce DDR5 requirements suddenly becomes an attractive proposition.

That shift helps explain Lenovo's suggestion that GPU-accelerated computing may now make more financial sense for some workloads. If an application can keep much of its working set in GPU-attached HBM, it may require significantly less DDR5 installed in the host system. With system DRAM now representing a much larger share of overall server cost than it did just a year ago, reducing memory capacity requirements can materially lower the price of deploying large-scale infrastructure.

Obviously, we don't know whether Lenovo's long-term outlook will prove accurate, but memory pricing has historically been cyclical, with periods of oversupply often followed by sharp corrections. With hyperscalers continuing to pour billions into AI infrastructure and memory vendors increasingly prioritizing high-margin enterprise products, the company believes the unusually inexpensive DRAM and NAND prices of 2024 and early 2025 may prove to have been an anomaly.

In a world where memory is no longer a commodity but a strategically valuable asset, customers are eager to sign long-term supply agreements (LTAs) with their suppliers to ensure a steady supply of 3D NAND and/or DRAM. Micron this week announced that it had signed 16 strategic customer agreements (SCAs), 14 of which are worth around $100 billion. Furthermore, the company expects to receive cash deposits and other commitments worth $22 billion, but has warned there is no foreseeable end in sight to the RAM crisis driving up PC component prices.

“14 of the 16 SCAs that we have signed have a cumulative revenue at minimum price per our contracts of approximately $100 billion over the remaining agreement term,” a statement by Micron reads. “Under the SCAs we have signed so far, we project to receive cash deposits and related financial commitments of $22 billion.”

Based on Micron’s claims, the company has about $100 billion of guaranteed baseline revenue already locked in under 14 of those 16 strategic customer agreements, assuming customers only buy the minimum committed volumes and only pay the minimum contract price. In reality, Micron can earn more if customers buy higher volumes or pay higher prices. Furthermore, Micron expects customers who signed these long-term SCAs to put up real money up front — or make equivalent binding financial commitments — as part of reserving future memory supply.

Micron claims it has signed strategic customer agreements with four 'very large customers' and three 'medium-sized customers,' which means that the contracts were inked with clients that previously did not commit to LTAs. The contracts are signed with a five-year term (except the automotive LTAs, which have a term of three years), from calendar 2026 to calendar 2030.

Micron claims that memory supply will be insufficient in 2027 and may improve gradually only in 2028. To that end, it is not surprising that its clients are willing to sign LTAs for 3D NAND and DRAM to ensure that they have enough memory for their products.

"With respect to supply, our customers are recognizing that supply shortages in memory and storage will take considerable time to improve," said Sanjay Mehrotra, chief executive of Micron, in prepared remarks. "Even as we expect industry supply to improve gradually in 2028, we currently do not have line of sight as to when memory supply will be able to catch up with increasing demand."

Normally, Micron and other memory producers inked LTAs with select clients only (read: with Apple, Nvidia). 16 LTAs is a lot for this kind of arrangement, and this looks like a business model shift for the company. It is noteworthy that the 16 signed contracts represent roughly 20% of Micron's DRAM volume and 33% of the company's NAND volume over the period through 2030. That said, Micron may sign more LTAs with more companies.

We're keeping a close eye on deals during Amazon Prime Day 2026 to find any RAM bargains to be had and adding them to the constantly-updated list below. RAM is only going to get more expensive. Inflation on prices is making it hard to find value in the memory market, but there are some deals you can still buy. You might be holding off for the market to stabilize, but signs indicate this problem is going to get worse in 2027, not better. You can also find good deals, often yielding the lowest overall RAM pricing, if you check our Prime Day RAM bundle page.

The memory shortage is taking hold, fueled by the massive AI data centers that are soaking up the world's memory stocks. This is causing a supply shortage, sending prices skyrocketing, and all indicators point to further price increases over the coming months. In fact, prices are expected to double throughout next year. Because the RAM market is very volatile right now, these deals tend to move quickly, so it's a good idea to act sooner rather than later so you don't miss out on a great opportunity. We're updating this page constantly to keep the deals fresh, but you will have to act fast to snag the last deals on memory we will likely see for at least a year, if not longer.

We've put together a handpicked list of the best options to make your shopping easier. These deals include everything from budget-friendly memory kits to premium options, like those featured on our best RAM page or at the top of our RAM benchmarks.

We carefully review offers from different retailers to find the best value for you, drawing on our extensive experience from thorough reviews, detailed benchmarks, and analysis of past prices. We keep a close eye on the latest RAM deals as they come up, highlighting the top choices we've found across various stores.

Top RAM Deals: Quick Links

• Amazon: Up to 18% off RAM at Amazon

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Also, you can join the Tom's Hardware deals Discord for up-to-the-minute hardware deals.

DDR2 contract prices rose 55% to 60% in the second quarter of the year and are projected to climb another 35% to 40% in the third, according to research published this week by TrendForce, pushing the AI-driven memory shortage onto a standard that first shipped in 2003 and that the three largest DRAM makers stopped prioritizing years ago. The increases come from buyers redesigning products around older memory to secure supply, and from a split among the handful of remaining DDR2 suppliers, with Winbond reducing output as ESMT expands it.

The shortage hasn’t hit DDR2 directly, but Samsung, SK hynix, and Micron have steered wafer capacity toward HBM and server DRAM to feed AI infrastructure spending, thinning the supply of mature-node parts, including DDR4. As DDR4 tightened, OEMs and ODMs began specifying DDR3 in its place, and some DDR3 designs were reworked to use DDR2, with each tier of buyers chasing whatever generation it could still source. The result of this is shortages moving down through successive generations, something we saw unfolding back in March, when earlier data showed DDR3 and DDR2 prices rising 20% to 40% in a single month.

This continues the market inversion we’ve watched unfold throughout the year, as DDR4 climbed past DDR5 on price despite being slower and older, and in which module makers and motherboard vendors restarted DDR4 production after the big three had moved to wind it down.

Winbond and ESMT are the two main remaining sources of DDR2 components, and they’re responding to the squeeze in different ways. Winbond is gradually cutting DDR2 production to shift capacity toward higher-margin DDR3, DDR4, and LPDDR4, while ESMT is doing the reverse, concentrating its wafer allocation at foundry partner PSMC on DDR2 to capture the demand Winbond is tossing aside. Taiwanese suppliers, including Nanya, are already struggling to match the volume of orders migrating down from DDR4, and because new capacity depends on slow process migration, Winbond's withdrawal removes supply faster than ESMT can replace it.

Of course, today’s PCs don’t use DDR2, so we’re likely to see the impact of these price increases landing in areas like embedded systems, networking equipment, industrial controllers, automotive electronics, and other long-lived devices that were designed around it and are too costly to requalify on newer memory generations like DDR4 and five.

The spread of rising contract prices to DDR2 suggests that we’re staring down the barrel of a very long-term DRAM shortage. Contract prices across the wider market are still rising with no sign of levelling off, and meaningful new capacity isn’t expected until late 2027 at the earliest as a best-case scenario.