Export controls have kept ASML's most advanced EUV lithography machines out of China. Instead, the country's chipmaking industry has relied on less-capable deep ultraviolet (DUV) lithography machines. By using multiple exposures on critical chip layers, these older machines are still capable of producing performant silicon. However, as multiple patterns are applied there are more chances for defects, longer manufacturing times, and higher bills. We spoke to experts like Chris Mack, co-founder and CTO of semiconductor firm Fractilia, to find out how much further DUV can go.

For years, extreme ultraviolet (EUV) lithography has been seen as China’s biggest choke point in the country’s attempts to build cutting-edge chips. The machines, made exclusively by Dutch manufacturer ASML, use 13.5nm-wavelength light to print some of the most intricate features found on modern processors. Sales of ASML’s EUV systems are subject to export restrictions, forcing Chinese manufacturers to squeeze ever more out of older deep ultraviolet, or DUV, lithography instead. The EUV gap alone between China and the West is at least half a decade, according to some analysts.

But even without access to EUV machines, China has gotten surprisingly far in recreating what it offers through existing technology.

Teardowns of Huawei’s Mate 60 Pro in 2023 found the phone’s Kirin 9000S processor had been made by SMIC using a second-generation 7nm-class manufacturing process without EUV. More recently, analysis of Huawei’s Kirin 9030 found SMIC had pushed its DUV-based process closer still to the density associated with 5nm manufacturing – although it continued to lag behind the leading processes used by TSMC and Samsung.

Multiple patterning

The trick is multiple patterning. Rather than trying to print an overly intricate chip layer in a single pass, Chinese manufacturers are dividing up the complex design into several simpler patterns. Repeat the process enough times and you can etch up something approximating the proper layer you intended.

The trick works. But according to lithography expert Chris Mack, co-founder and CTO of Fractilia, asking whether a chip can be made without EUV overlooks the trade-offs manufacturers make in order to do it.

“When this transition first began, what everyone in the industry said as conventional wisdom is that cost-wise, three exposures on a 193 immersion tool cost about the same as one exposure on an EUV tool,” Mack said in an interview with Tom’s Hardware Premium. “At three, it was about even,” Mack explained. “But as soon as you hit four masks – 193 masks being replaced by one EUV mask – then EUV became more cost-effective.”

It’s also likely to produce a higher quality product with fewer defects. Each time a wafer is patterned, that new pattern has to line up perfectly with everything that’s already been etched beneath it. The more individual exposures needed to produce a single layer, the more opportunities there are for things to go wrong. “If you have, say, four 193 masks, you've got all those different overlays, and you've got all these different process variations that start to accumulate,” Mack said.

Chip designers can try and avoid that by leaving more space around features so the finished processor can actually be manufactured reliably. But that means the chip ends up bigger – and bigger chips become expensive very quickly. Making each die larger means fewer fit on every wafer, and wafers cost a lot of money – tens of thousands of dollars each.

“You don't sell wafers, you sell die,” Mack said. “The question is: how many die can I fit onto that wafer, and how many of those die yield, and therefore how many chips can I sell per wafer?”

The efficiency gap

There is some evidence of what that efficiency gap can look like in practice – albeit in memory rather than logic chips. In a June report, Morgan Stanley estimated that Chinese DRAM manufacturer CXMT was producing only around one-third as many bits per wafer as Western competitors. The analysts believed the older process node only accounted for around a third of that shortfall, but said access to lithography was a “hard ceiling” on Chinese memory development. “For advanced logic chips, in theory there could be other innovations to engineer around EUV, but they are not likely to be very efficient and effective,” said Douglas Fuller, a researcher at Copenhagen Business School, in comments to Tom’s Hardware Premium.

It is also why claims that China has reached a particular semiconductor process “node” need to be treated with caution. “If somebody says it's X node – the seven nanometer node, the five nanometer node, the three nanometer node – these words almost have no meaning,” Mack said.

That can be seen in SMIC’s latest chips. Reporting suggests its N+3 process represents meaningful progress towards 5nm-class manufacturing – but the actual measurements show it remains significantly less scaled than established 5nm processes from Samsung and TSMC. That doesn’t mean DUV has reached the end of its useful exploitation.

Stretching DUV's efficacy

Micron is an example of how far DUV can be stretched, producing competitive DRAM chips using DUV, multiple patterning and tight process control. Its 1-alpha generation of chips was developed without EUV. “They pushed 193 farther than any of the other memory makers did,” Mack said. “They were able to make very competitive chips with 100% 193 compared to Samsung and Hynix making them with many layers of EUV.”

Morgan Stanley believes CXMT’s planned move to 1-alpha DRAM – which it wants to use for HBM3e – is achievable without access to EUV, citing Micron as evidence. Indeed, “by the end of the decade, advanced packaging will allow firms to use DUV to produce the latest generations of DRAM,” reckons Fuller.

Micron also designed its products around the manufacturing technology available to it, rather than simply trying to recreate an EUV process on older equipment – something which could be a useful lesson for Chinese manufacturers. “If the entire ecosystem of 193 immersion were available to China,” Mack explained, “then they could probably push a long way with 193 multiple patterning, especially if they optimise designs for the fact that they're going to be using that.”

But Micron was making memory, whose highly repetitive structures make close co-ordination between chip design and manufacturing easier than it is for the much more complicated logic processors found in phones and computers.

“Memory is a lot easier than logic,” Mack said.

And even Micron eventually concluded that EUV was worth using. Its newer 1-gamma DRAM process uses EUV lithography, with Micron saying the technology helps it achieve more than 30% greater bit density per wafer than its preceding 1-beta generation.

EUV is hardly a magic wand, either. Mack points to stochastic effects – tiny random variations caused by the small number of photons involved in an exposure – which mean manufacturers can improve pattern control by increasing the EUV exposure dose. But it also pushes the cost back up quickly.

Because of that, Mack believes there is ultimately a limit to how far multiple patterning can economically substitute for EUV. “I would be hard pressed to really believe that a three nanometer or a two nanometer node is going to be economically viable without EUV,” he said.

That doesn’t mean Chinese chipmakers simply hit a technological wall and stop. They can keep pushing DUV while accepting larger dies, poorer yields, longer manufacturing times – or some combination of all three.

They can also throw capacity and money at part of the problem. Morgan Stanley assumes CXMT remains stuck on its 1-alpha process without EUV, yet still increases its share of global DRAM bit supply from 14% in 2026 to 16% in 2028 simply by building more greenfield capacity. The bank also expects China’s AI chip self-sufficiency to rise from 42% in 2025 to 70% by 2030 through new advanced-node capacity, improving yields and heavy state support – while EUV, HBM and advanced software leave a persistent gap. And so without EUV, the experts reckon China can only get partway to bridging the gap with the West. ““I would be hard pressed,” said Mack, “to really believe that a three nanometer or a two nanometer node is going to be economically viable without EUV.”

Data center energy demand is shooting constantly upwards. By 2030, some 945TWh of electricity is expected to be used to meet AI’s demand; the International Energy Agency believes — that's as much electricity as Japan uses today. The energy crunch is inescapable, and the industry’s answer has largely been to focus on the physical: build more efficient GPUs and secure more power supply from an already tight grid. But is that myopic focus on hardware actually worth it? Instead, could most of the work running on those machines be cut back to save power?

Average power usage effectiveness (PUE) has barely changed for six successive years, according to the Uptime Institute’s 2025 survey. PUE can show whether cooling and power systems are wasteful, but doesn’t account for whether the software running on the servers is doing useful work. And given servers account for around 60% of electricity demand in a modern data center, while cooling ranges from about 7% in an efficient hyperscale site to more than 30% in a less-efficient enterprise facility, focusing on eking out more efficiency from the software side of the equation seems sensible.

“The answer to what seems to be the core question – ‘Can software or algorithms meaningfully help with power and energy?’ – is yes, 100%,” said Jae-Won Chung, a PhD candidate in computer science and engineering at the University of Michigan and researcher with the ML.Energy initiative, in an interview with Tom’s Hardware Premium.

Chung suggests computing systems should be seen as a stack with hardware at the bottom, backed up by systems software, algorithms and applications. The hardware end of that equation is the hardest bit to tackle: chips are slow and costly to replace. But the other three layers are easier to change, and any gains in efficiency made there can compound.

ML.Energy’s tests of the Alibaba Qwen 3 235B A22B Thinking model suggest that running inference in FP8 – a slightly lower-precision format – consumed a third less energy than bfloat16 versions on problem-solving tasks. Chung’s own Perseus training optimiser identifies parts of a large-model training job that have less work to do, then slows them so they finish alongside busier parts. The system cut training energy by up to 30% without reducing throughput or changing the hardware.

This isn’t a tweak around the edges being made by tinkerers: some of the biggest GPU firms are doing something similar. Nvidia’s Blackwell power profiles fine-tune everything from GPU compute and memory frequencies, power limits, NVLink states and cache settings to fit the workload. Nvidia believes that can save up to 15% of energy while retaining 97% or more of overall performance, allowing power-constrained facilities to run more GPUs, raising throughput by as much as 13%.

‘The loudest rack in the room’

Chetan Visrolia, business development manager for data center infrastructure at SHI, said in an interview with Tom’s Hardware Premium that the most obvious waste he encounters is often legacy equipment supporting old code. “It is always the lowest-hanging fruit for quick savings,” he said. “It can easily be found in any data center, as it is the loudest rack on the floor.”

Cloud instances can also be made a smarter size, and AI prompts that are repeatedly used can be stored in cache rather than recomputed on the fly. There are also efficiencies to be made by getting small models to handle routine requests while holding back the larger ones for harder tasks. At the same time, better batching and compilers can raise accelerator utilisation, and crunching down prompts while throwing limits on outputs can also tamp down the number of tokens processed.

Software can also change when and where electricity is drawn. Sophie Hall, a doctoral student at ETH Zurich’s Automatic Control Laboratory who has studied workload shifting across Google’s global data-center fleet, argues in an interview with Tom’s Hardware Premium that electricity consumption isn’t necessarily the main problem.

“It’s more like: when do they use it, where do they use it, and how is it interacting with the grid?” she said. If batch jobs aren’t time-sensitive, they could be delayed until local demand falls or routed to a region with spare capacity and lower-carbon electricity. Hall’s research uses day-ahead planning and real-time scheduling to respond to grid signals while preserving performance guarantees.

Taking that kind of action was less necessary when hyperscalers built way more capacity than they actually needed and the grid wasn’t a bottleneck, Hall said. But the massive demand for AI has changed the equation.

There are limits, though: individual countries’ data sovereignty rules can prevent a workload from crossing borders, while moving large datasets across networks is something that inference providers may be wary of in case things go wrong. “The data needs to literally, physically, geographically move to a different location,” Hall said. “That’s not that easy.”

The scale of the data center demand powered by AI means that software isn’t a silver bullet or a substitute for better chips and new electricity infrastructure. But it can act as a control layer that squeezes out every last drop from those increasingly expensive assets, while also helping shift demand to places where there is more capacity.

Jevons ’ paradox is also at play, and needs to be considered when thinking about making systems run better. Efficiency doesn’t reduce a facility’s electricity use if each watt saved gets used up generating even more tokens. “Power is the core bottleneck in AI data centers,” said Chung. “We really want to make the best use of every watt we consume.”

Put to work on different tasks, AI can do a good many specialist skills that even just a few months ago wouldn’t have been thought possible. AI is beginning to take on some of the work required to design the chips that power AI, way beyond simple optimisation. But that brings a potentially expensive problem: what happens if an AI ends up generating a design that infringes somebody else's patent, which then ends up in thousands of chips rolling off production lines? Tom's Hardware Premium spoke with experts like Domenec Forte, professor of electrical and computer engineering at the University of Florida, and Simon Moore, professor of computer engineering at the University of Cambridge, to learn more about a looming issue that could broadly impact the AI chip design market.

This week, Synopsys announced a suite of AgentEngineer tools capable of carrying out long-running tasks that could verify and implement chips, as well as planning analog design and manufacturing. The company said it had more than 50 customer engagements already underway, and planned to offer the tech for general availability by the end of the year.

Synopsys isn't alone in discovering the ability of AI to do such tasks. Competitor Cognichip says its ACI platform can generate specifications and RTL, then automatically produce verification plans and testbenches. And in China, Empyrean Technology recently claimed an AI agent reduced the time taken to complete one circuit layout task from four weeks to one. Even the big AI labs are getting in on the act: OpenAI says its models helped it and Broadcom develop Jalapeño, its first custom inference chip, from initial design to tape-out in just nine months.

It all poses difficult questions for the chip design industry – though not just about whether the sector will remain strong. It’s also about whether AI is a suitable replacement for human ingenuity. The industry relies heavily on intellectual property, and it’s not yet clear what happens when an AI designs something that somebody else already owns. Rather than designing every component of a chip from scratch, companies routinely license processor architectures, controllers, and other memory technologies rather than reinvent the wheel. Arm alone generated nearly $5 billion in its 2026 financial year, which came roughly half from licensing and other revenue and half from the royalties on that. Synopsys makes money that way too, selling a substantial portfolio of "silicon-proven" IP alongside its chip design software.

The AI copied my homework

But by putting AI to the task, some of those blocks could become far easier to create – and working out where they came from far harder. "It mostly amplifies existing problems," said Domenec Forte, professor of electrical and computer engineering at the University of Florida, whose research includes AI-enabled chip-design tools and semiconductor IP protection, in written comments to Tom’s Hardware Premium. "AI can spread a copied design or infringed patent across thousands of chips before anyone notices and without anyone even intending it,” he said.

Copying wouldn’t be as blatant as feeding an Arm core or another piece of proprietary RTL directly into a model. Instead, AI’s skill is in ingesting huge amounts of literature from academic papers and patent applications, then constructing lookalike designs. And in a space where power constraints, performance challenges, and a limited physical area all combine alongside mandated standards all have to follow, there are only a finite number of feasible designs that AI can reach quicker – inadvertently copying others’ homework. "Even a circuit that adds two numbers draws from a well-documented catalogue of textbook designs," said Forte. "Ask for the fastest one, and you'll likely land on a design someone has already published."

That creates a provenance problem for chips, because human engineers generally document and can explain where their ideas came from and which IP was licensed. AI might not have that same traceability. Existing tools can identify close copies, Forte said, but designs can be rewritten or run through synthesis tools that transform their implementation while leaving the underlying function intact.

Forte suggests IP owners could eventually deposit encrypted versions of their designs into a shared repository, allowing trusted agents to check whether newly generated hardware overlaps with existing IP without exposing the originals. He’s less convinced by watermarking, which he argues could be removed or forged. International standards could help somewhat: IEEE 1735 defines methods for encrypting electronic-design IP and managing the rights attached to it. But Forte argues standards like it may now need to go further, defining what AI agents can access, retain, and learn from while operating inside electronic design automation tools.

An abundance of caution

That all might suggest there’s a free-for-all when it comes to AI designing new chips, and potentially ripping off – advertently or not – other designs. But that’s not the case, for a simple reason. The semiconductor industry is unusually cautious about new design techniques because software can be patched, whereas fabricated silicon can’t. “Once you ship the chip, you ship the chip, and you can't change the transistors,” said Simon Moore, professor of computer engineering at the University of Cambridge, said in an interview with Tom’s Hardware Premium.

Moore estimates verification now accounts for more than half of the effort involved in getting many chips out of the door, while established verification tools can tell engineers whether an AI-generated test actually improves coverage. Getting that AI to conduct tests, probe possible failure points, and check results at scale is “a bit of a no-brainer," said Moore. However, allowing AI to make architectural decisions, which are much harder to undo, is where most manufacturers are drawing the line.

That same caution explains why licensed IP may survive the onslaught of AI-generated content, even if the tech is capable of generating technically similar blocks. Buying a block from Arm, Synopsys, or another established vendor comes with the history of the companies, and the assurance that it’s gone through the relevant verification and standards compliance checks.

So could AI reduce reliance on licensed IP? “For routine building blocks, probably yes,” said Forte. “But a licensed IP block is much more than its design files.”

And if engineers increasingly have to ask not only whether a design works, but where it came from and whether somebody else already owns part of it, provenance may become something semiconductor companies are all the more willing to pay for. “I'd treat an AI designer like a brilliant new hire,” said Forte. “Fast and talented, but everything it produces gets checked.”

The memory chip that makes a router remember how to be a router is a world away from the sleek GPUs that are attracting eye-popping investments and alarming valuations, as well as sending stock markets shooting upwards. They’re small, historically have been cheap, and are based on technology that has been around for years.

But despite being a world away from GPUs, the price of these often overlooked chips is skyrocketing, thanks to the all-encompassing memory price crisis caused by the AI boom.

While public and press attention has focused on the expensive chips, there’s an equally large impact beginning to be felt on older, less attractive memory chips. HBM is vital for AI accelerators, while DRAM and high-capacity NAND are being swallowed up by rapidly expanding data centres. A June report from Morgan Stanley reckons memory prices have risen more than sixfold over the last year, breaking with decades in which memory became steadily cheaper as production increased.

It’s not just HBM and DRAM that’s being affected. The crunch is also spreading down into much older forms of memory, including NOR flash and single-level cell, or SLC, NAND. Morgan Stanley expects NOR flash to remain undersupplied through 2026, while JPMorgan has warned its forecasts don’t fully capture a potential supply crunch in SLC NAND. The effects are already showing up in prices. TrendForce says contract prices for both NOR flash and SLC NAND rose by more than 100% during the first half of 2026, while it expects SLC NAND prices to rise another 120% to 170% in the second half of the year compared with the first half.

Picking winners

An increase in prices will have an impact on the tech we use day in, day out. NOR flash is commonly used to store boot and program code, and is a core part of automotive, industrial, and networking equipment. SLC NAND is deployed across a number of uses because of its reliability and endurance when placed in embedded hardware with long lifespans.

Both are vital. And both are being overlooked in favour of higher-margin chips — pushing the supply crunch to tech that previously never faced any issues. “The SLC NAND market is probably under a billion dollars a year,” said Jim Handy, a semiconductor and SSD analyst at Objective Analysis, in an interview with Tom’s Hardware Premium. That tiny scale adds up to a big problem, because it disincentivises any new investment.

“What you've got going on is a purely economic phenomenon,” said Handy. Hyperscalers and cloud providers are “all trying to outspend each other”, pouring unprecedented sums into semiconductors to build AI infrastructure. That willingness to spend big means the most profitable customers naturally move to the front of the queue.

Companies including Nvidia, Broadcom and Marvell need huge amounts of semiconductor manufacturing capacity for chips destined for AI systems. “They’re sucking up all of the wafers,” says Handy. “And then the companies who make NOR flash and SLC are having a hard time getting wafers to build their product, and so they have to raise prices.”

The problem is even starker in the NAND market. Bryan Ao, research manager at TrendForce, told Tom’s Hardware Premium in an interview that major NAND manufacturers, including Micron, Kioxia and SK Hynix, have been cutting the wafer capacity devoted to SLC because they can make considerably more money using it for newer NAND technologies. Ao estimates that a 12-inch wafer devoted to mainstream NAND can ultimately generate close to $20,000 in revenue. Use the same space to produce SLC and the figure is closer to $6,000 to $8,000.

Even if they wanted to, smaller SLC suppliers in China and Taiwan can’t just spin up new production. Lead times for some semiconductor manufacturing equipment have stretched to between 12 and 15 months, said Ao. The result is what he calls “severe undersupply”.

Big prices, big returns

BNP Paribas forecasts the average NAND price will hit $279.50 per terabyte during 2026, up from $73.10 in 2025. JPMorgan expects the memory shortage to persist for at least another two years, with customers getting just 70% to 80% of their orders fulfilled. TrendForce says manufacturers are shifting capacity towards advanced, higher-value memory products, with mature processes increasingly squeezed as a result.

There are some alternatives available. Kioxia says its serial SLC NAND is an alternative to NOR flash. But moving an existing industrial or networking product onto a different chip can itself require engineering work and qualification. Nor is there much incentive for memory manufacturers to fix the problem by building new SLC capacity – which means manufacturers are unlikely to invest billions in capacity whose useful market may disappear. That creates an unusual trap: there may not be enough demand to justify new factories, but there is still more demand than the shrinking supply can satisfy.

Hardware manufacturers can eat the higher component bill and accept lower margins, or pass it on. “We'll just have to either have lower margins, or we'll have to raise the prices to the consumer,” Handy said.

An ongoing issue

The problem is one that seems to have no solution – at least in the short term. Ao expects memory prices to remain high over the next five years and does not expect them to return to 2023 or 2024 levels. That broadly fits with the structural nature of the shortage identified by TrendForce, which says there are no significant capacity expansion plans for NOR flash or SLC NAND.

Handy sees one possible way out, but it is hardly reassuring. “As long as the race between the hyperscalers keeps up to spend, then it will continue to be an issue,” he said.

Handy compares the AI buildout to the internet infrastructure boom of the late 1990s. Rather than enough capacity eventually arriving to restore balance, he thinks spending may simply overshoot what the market can economically support.

“I'm expecting the same kind of a thing to happen here that we've got too many people spending too much money on AI, and not really making any return on it yet,” he said.

Until then, the least exciting memory chips in a computer may become some of the hardest to replace. Or, as Ao put it: “Pretty much we have to get used to this high price, no matter which segment of memory.”